The present invention relates to the fabrication of integrated circuit semiconductor devices. More particularly, the invention as now disclosed and claimed encompasses a photolithographic mask implemented procedure for forming planarized silicon dioxide (oxide) filled trenches of arbitrary width between active regions in a semiconductor substrate.
The need for field isolation between adjacent electrically active regions together with the desire for greater planarity of wafer surfaces, which planarity provides improved photolithographic accuracy and minimizes step coverage problems, has led in recent times to the use of semi-recessed field oxides. A commonly known and still extensively used semi-recessed technique, the LOCOS process, was introduced in the the early 1970's and has until recently remained the preferred technique for isolating active regions in semiconductor wafers. However, with the increasing density of active devices on semiconductor wafers, the area penalty arising from the bird's beak or bird's head effect in the LOCOS process has become unacceptable. The volume expansion of substrate regions during thermal oxidation in accordance with the LOCOS process has made it difficult to develop refinements which improve the planar character of the wafer topology. Furthermore, with the smaller dimensions of interconnect layers, planarity of the field isolation dielectric has become even more important, from the perspective of step coverage.
To overcome the deficiencies inherent in LOCOS type semi-recessed field oxide processes, researchers have proposed various trench oxide isolation techniques. Though processes for forming planar oxide filled trenches are known for trenches of specified shapes and dimensions, techniques for forming planar trench structures of arbitrary widths have yet to evolve to a stage of flexibility suitable for routine implementation. For example, U.S. Pat. No. 4,104,086 discloses a technique for using conformal oxide to fill narrow trenches having specifically defined depths and sidewall angles. According to that teaching, conformal silicon dioxide is deposited on all exposed substrate surfaces, including the trench interior, until the thickness of the oxide causes a closure of the trench cavity.
In an attempt to deal with trenches having varying depths and sidewall angles, the inventors in U.S. Pat. No. 4,139,442 proposed a different trench isolation technique, according to which adjacent narrow trenches of fixed relationship are simultaneously formed in all trench regions. The silicon projections between adjacent trenches are thereafter converted to silicon dioxide by conventional oxidation techniques and then, if necessary, further filled with deposited oxide. However, the oxidation process remains subject to the variables of the volume expansion.
Another technique, involving the creation of thin silicon walls between adjacent and simultaneously formed trenches, appears in U.S. Pat. No. 4,211,582. Unfortunately, the proposed approach also requires the careful use of significant oxidation, and concludes with a nonplanar surface topology. Although trenches of arbitrary width can be created and filled with a dielectric using the technique, the complexity and above noted deficiencies are clear detractors.
Another trench isolation process is disclosed in U.S. Pat. No. 4,238,278. There, conformally deposited polysilicon is used to fill the trench voids and, after planarization of the surface, is oxidized to establish continuity of the dielectric across the mouth of each trench region. Wider trenches are formed with a second etch of the substrate and an oxidation of the substrate silicon in the area of the second etch. However, exact implementation of the latter technique is somewhat speculative in that there are exposed regions of polysilicon, silicon dioxide, and monocrystalline silicon which must be selectively masked and etched to implement the procedure, while the specific teaching thereof is conspicuously omitted. The process disclosed in U.S. Pat. No. 4,238,278 is also deficient by virtue of the residual polysilicon it inherently retains, as depicted in FIG. 4 thereof. Experience has shown that such residuals may act as long term charge trapping sites, in the sense of nonvolatile floating gate devices. Furthermore, such polysilicon residuals increase the capacitive coupling for interconnect lines passing in close proximity thereto.
Given the complexities and deficiencies of the various procedures set forth in the references noted hereinbefore, the most commonly practiced techniques for creating trench isolation structures filled with oxides utilize spin-on coatings. According to the common feature of such techniques, the uneven surface following oxide deposition in trenches of arbitrary width is first covered by a moderate viscosity spin-on coating and is then reactive ion etched in an environment providing a 1:1 etch ratio of the coating to the underlying oxide dielectric. Thereby, at least conceptually, the planar nature of the surface is transferred to the dielectric layer. Unfortunately, with arbitrary width trenches the spin-on coating must be of sufficiently low viscosity to flow into minimum width trenches while retaining the planarity desired in the face of surface tension forces in wide trench areas. These characteristics are difficult to achieve over an entire wafer if the tolerances required for submicron devices are to be obtained consistently. A recent variation to the use of spin-on coating is disclosed in U.S. Pat. No. 4,505,025. This refined technique remains subject to the effects of non-unity etch ratios as well as the effects of mask misalignments.
Therefore, there remains a need for a trench oxide isolation process which avoids the stress problems of thermal oxidation, insures the absence of conductive residue within the trench region, and provides a planar active region surface, yet is implemented without undue design or fabrication complexity.